Listar por autor "Espejo Meana, Servando Carlos"
Mostrando ítems 1-20 de 58
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Ponencia
A 0.5 /spl mu/m CMOS CNN analog random access memory chip for massive image processing
(Institute of Electrical and Electronics Engineers, 1998)An analog RAM has been designed to act as a cache memory for a CNN Universal Machine. Hence, all the non-standard chips ...
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A 0.8-μm CMOS two-dimensional programmable mixed-signal focal-plane array processor with on-chip binary imaging and instructions storage
(Institute of Electrical and Electronics Engineers, 1997)This paper presents a CMOS chip for the parallel acquisition and concurrent analog processing of two-dimensional (2-D) ...
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A 1000 FPS at 128×128 vision processor with 8-bit digitized I/O
(Institute of Electrical and Electronics Engineers, 2004)This paper presents a mixed-signal programmable chip for high-speed vision applications. It consists of an array of ...
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A Bio-Inspired Two-Layer Mixed-Signal Flexible Programmable Chip for Early Vision
(Institute of Electrical and Electronics Engineers, 2003)A bio-inspired model for an analog programmable array processor (APAP), based on studies on the vertebrate retina, has ...
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A Chaotic Switched-Capacitor Circuit for 1/f Noise Generation
(Institute of Electrical and Electronics Engineers, 1992)A switched-capacitor circuit is reported for the generation of 1 / fYnoise. The circuit is described by a chaotic first-order ...
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Ponencia
A countinuous-time cellular neural network chip for direction-selectable connected component detection with optical image acquisition
(Institute of Electrical and Electronics Engineers, 1994)This paper presents a continuous-time Cellular Neural Network (CNN) chip [1] for the application of Connected Component ...
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A Front-End ASIC for a 3-D Magnetometer for Space Applications by Using Anisotropic Magnetoresistors
(Institute of Electrical and Electronics Engineers, 2015)This paper presents an application-specific integrated circuit (ASIC) aimed for an alternative design of a digital 3-D ...
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Ponencia
A mixed-signal early vision chip with embedded image and programming memories and digital I/O
(The International Society for Optical Engineering - SPIE, 2003)From a system level perspective, this paper presents a 128 × 128 flexible and reconfigurable Focal-Plane Analog Programmable ...
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Ponencia
A Model for VLSI implementation of CNN image processing chips using current-mode techniques
(Institute of Electrical and Electronics Engineers, 1993)A new Cellular Neural Network model is proposed which allows simpler and faster VLSI implementation than previous models. ...
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A multimode gray-scale CMOS optical sensor for visual computers
(Institute of Electrical and Electronics Engineers, 2002)This paper presents a new multimode optical sensor architecture for the optical interface of Visual CNN (cellular neural ...
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Ponencia
A one-transistor-synapse strategy for electrically-programmable massively-parallel analog array processors
(Institute of Electrical and Electronics Engineers, 1997)This paper presents a linear, four-quadrants, electrically-programmable, one-transistor synapse strategy applicable to the ...
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Ponencia
A processing element architecture for high-density focal plane analog programmable array processors
(Institute of Electrical and Electronics Engineers, 2002)The architecture of the elementary Processing Element - PE- used in a recently designed 128×128 Focal Plane Analog ...
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A switched-capacitor broadband noise generator for CMOS VLSI
(Institution of Engineering and Technology, 1991)A switched-capacitor circuit is reported for the generation of broadband white noise in MOS VLSI. It is based on the ...
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Ponencia
A versatile sensor interface for programmable vision systems-on-chip
(The International Society for Optical Engineering - SPIE, 2003)This paper describes an optical sensor interface designed for a programmable mixed-signal vision chip. This chip has been ...
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Ponencia
ACE 16k based stand-alone system for real-time pre-processing tasks
(The International Society for Optical Engineering - SPIE, 2005)This paper describes the design of a programmable stand-alone system for real time vision pre-processing tasks. The system's ...
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Ponencia
ACE16K: A 128×128 focal plane analog processor with digital I/O
(Institute of Electrical and Electronics Engineers, 2002)This paper presents a new generation 128×128 focal-plane analog programmable array processor (FPAPAP), from a system level ...
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Ponencia
ACE16k: A programmable focal plane vision processor with 128 x 128 resolution
(European Conference on Circuit Theory and Design, 2001)This paper presents a new generation 128x128 Focal Plane Analog Programmable Array Processor (FPAPAP), from a system ...
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ACE16K: The Third Generation of Mixed-Signal SIMD-CNN ACE Chips Toward VSoCs
(Institute of Electrical and Electronics Engineers, 2004)Today, with 0.18-μm technologies mature and stable enough for mixed-signal design with a large variety of CMOS compatible ...
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An 0.5-μm CMOS analog random access memory chip for TeraOPS speed multimedia video processing
(Institute of Electrical and Electronics Engineers, 1999)Data compressing, data coding, and communications in object-oriented multimedia applications like telepresence, computer-aided ...
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Ponencia
Analog weight buffering strategy for CNN chips
(Institute of Electrical and Electronics Engineers, 2003)Large, gray-scale CNN chips employ analog signals to achieve high-density in the internal distribution of the template ...